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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 1. Register Address Map
REGISTER
Port P1 or INT Output
Port P2 or OSCIN Input
Port P3 or OSCOUT Output
Port P4
Port P5
Port P6
Port P7
Port P8
Port P9
Configuration 26
Configuration 27
Ports P2–P5 Configurable Logic CLA0
Ports P6–P9 Configurable Logic CLA1
Write Ports P2–P5 Same Data; Read P2
Write Ports P6–P9 Same Data; Read P6
FACTORY RESERVED (Do not write to these registers)
CLA0 and CLA1 Configurable Logic Enable
CLA0 and CLA1 Configurable Logic Lock
Configuration 67 Lock, Ports P1–P5 Lock
Ports P6–P9 Lock
FACTORY RESERVED (Do not write to these registers)
ADDRESS
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x26
0x27
0x28
0x29
0x3C
0x3D
0x3C–0x3F
0x70
0x71
0x72
0x73
0x00
AUTOINCREMENT ADDRESS
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A or 0x4A
0x27
0x28
0x29
0x2A
0x3D
0x3E
0x3F–0x40
0x71
0x72
0x73
0x74
0x01
POR STATE
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0xCC
0x8F
0x00
0x00
0x80
0x80
0x00
0x00
0x00
0x00
0xF0
0x80
Table 2. Power-Up Register Status
REGISTER
POWER-UP CONDITION
ADDRESS REGISTER DATA
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Ports P1–P9
Configuration 26
Configuration 27
Ports CLA0 to CLA1
CLA0 to CLA1
Configuration 27 Lock,
Ports P1–P5 Lock
Ports P6–P9 Lock
Ports P_ are V LA -referred input ports with interrupt
and debounce disabled
RST does not reset registers or counters; blink period
is 1Hz; transition flag clear; interrupt status flag clear
Ports P1–P9 are GPIO ports; bus timeout is
disabled
Default gate structure
CLA not enable
Configuration 27 is not locked;
ports P1–P5 are not locked
Ports P6–P9 are not locked
0x01–0x09
0x26
0x27
0x28–0x29
0x70
0x72
0x73
1
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
8
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